RS-232, the ACIA and the Apple®


  1. Introduction
  2. The RS-232 Serial Link
  3. The ACIA
  4. The Apple Expansion Slot
  5. Monitor Exercises
  6. Hardware Considerations
  7. References


This article deals with three related subjects. First, the RS-232 serial data link. Second, the Motorola 6850 ACIA, a typical device connecting the external RS-232 circuits with the computer busses, and finally, the expansion slots on the Apple II that permit cards containing things like ACIA's to interface them with the computer. Similar studies can be done with an IBM PC with an ISA bus and the 8250 ACIA, which IBM chose for its Asynchronous Communications Adapter. Information for the PC serial interface is much easier to come by, since it is still current. Actual experiments are suggested, which can be carried out easily only on the earlier equipment typical of the 1980's. Modern computer systems are ill-adapted to learning about computers, especially the hardware-related aspects. If you have some of this earlier equipment, as I have, you are very fortunate.

Hex numbers sometimes appear preceded by a $ in what follows, sometimes not, but should be easy to recognize by the context. A signal that is "active low" is followed by an apostrophe, as in DEVICE SELECT'. This means that it may normally be a TTL high level, and is brought to a TTL low level to signal a certain condition. This is usually indicated by an overbar, and sometimes by a leading /. Commands typed in at the command line following a prompt, such as ] or *, are followed by Enter (Return) to execute them, which is not explicitly noted.

The reader will understand more if familiar with 6502 assembly-language programming and the Apple II, or with 8086 assembly-language programming and the IBM PC, if using that system. This includes Monitor use on the Apple, or DEBUG use on the IBM PC. The present subject is one of the places where programming, or software, interacts with hardware in a very significant way. The designer must consider both for the best outcome. The driver program for the 7710 Asynchronous Serial Interface for the Apple II is analyzed in some detail, to show what has to be done and how to do it.

It is very useful to have an actual, funtioning card to serve as an example. In this case, we use the California Computer Systems 7710 interface for the Apple II. From an example, it should be very easy to make a plug-in card for a 6520 parallel interface adapter, for example, providing byte input and output, or a digital/analog converter. Apple slots are easy to use, but timing is critical. IBM slots require a little more work, but timing is reliable.

The RS-232 Data Link

The RS-232 data link is a full-duplex ("four-wire") link over which data can pass simultaneously in both directions. The EIA RS-232-C standard will be used here, but other protocols are available. Later, but similar, standards are EIA-232-D and CCITT V.28. The RS-232 link uses voltage levels of +3 to +15 V (SPACE, data 0, on, green) and -3 to -15 V (MARK, data 1, off, red) for the two logic states. This link is effective over greater distances than TTL levels, and is much less susceptible to interference. Six circuits, 2 data and 4 handshaking, and ground are normally used. The ends of the link are usually connected by a 25-conductor shielded cable with DB-25 connectors of opposite sex on the two ends. Since the link only uses about 7 wires, DB-9 connectors are frequently used now for serial links, with correspondingly simpler cables. If you work with serial links, you should provide yourself with a 25-to-9 pin adapter, as well as DB-9S and DB-9P connectors for making adapters, as described below.

This interface was originally used for the communication between a modem on the telephone line and a computer, which the terminology reflects. One end was called the Data Communications Equipment, or DCE (the modem), and the other was called the Data Terminal Equipment, DTE (the computer). The DCE was also called the Data Set. The standard connector was a 25-pin DSUB connector. The signal on each pin has a name. Data is transmitted from DTE to DCE on pin 2, and from DCE to DTE on pin 3. The levels (like those of all the signals) are relative to ground on pin 7. The pinout for a DB-9P connector is shown at the right. The numbers are the equivalent pin numbers for a DB-25. Pin 22 is RI, ring indicator, for telephone connections.

Handshaking lines are used to control when data can be sent. DTE uses a signal called RTS on pin 4, while DCE uses a signal called CTS on pin 5. One way of using these signals is to prevent the DCE from sending unless RTS, controlled by the DTE, is active (low). The DTE is prevented from sending unless CTS, controlled by the DCE, is active (low). One output and one input bit is provided on the ACIA for this purpose. The ACIA also checks another input, called CD. On DTE, this input is called DSR, and is on pin 6. On DCE, it is DTR and is on pin 20. In the diagram, this signal is held permanently at +12 V or active by a pullup resistor, so it contains no information. Indeed, it can be omitted and the CD input itself tied low. It was used in more complex links to reflect conditions on the telephone line, which are of no importance here. RTS and CTS are sufficient to provide handshaking.

Most RS-232 links are used in one direction at a time. Data is transmitted continuously in one direction, while an occasional handshaking byte is transmitted in the reverse direction when necessary. This is usually called an XON/XOFF protocol. XOFF = CTRL-S = DC3 = $13, and XON = CTRL-Q = DC1 = $11 are the handshaking bytes used. Software handshaking of this kind is usually more convenient than hardware handshaking, but both kinds are generally available. The bit rate and the data format must be the same at both terminals.

The connection of two ACIA's (discussed in the next section) to form a serial link is shown at the left. The numbers on the conductors are the pin numbers of the DB-25 connector to which they are attached. That is, pin 2 is connected to the TD of the left ACIA, and to the RD of the right ACIA. The conductor in the cable is connected to pin 2 at each end. This connection makes the left ACIA a DTE, and the right ACIA a DCE. DTE and DCE are just names; a DTE transmits through pin 2, a DCE through pin 3. A DTE should have a DB-25P plug, and a DCE a DB-25S socket, as shown in the diagram. The DB-25S of the connecting cable fits the DTE, while the DB-25P of this cable fits the DCE. Although the conductors seem to cross, TD of the DTE connects with RD of the DCE through the conductor connected to pin 2 on both ends of the cable from the way the connectors are wired. Note the inverters on the line drivers and line receivers. They make a TTL logic 0 a SPACE or positive voltage, and a TTL 1 a MARK or negative voltage. The "active" or "on" state is usually TTL 0 and SPACE.

The circuits connecting TTL and RS-232 levels are called line drivers and line receivers. Originally, Motorola supplied the 1488 quad driver and the 1489 quad receiver, while Texas Instruments supplied not only these, as the 75188 and 75189, but also the 75150 dual driver and 75154 quad receiver. These must be supplied not only with the TTL +5 supply, but also with ±12 for the serial link. When other devices, such as memory, no longer required the ±12 supplies, it was inconvenient to provide a power supply just for the RS-232 link. Therefore, chips were developed like the MAX232 that included two transmitters, two receivers, and switched-capacitor ±10 supplies. This popular chip is second-sourced as the TC232 and others. This was enough for TXD, RXD, RTS and CTS, which is all that is really needed for a basic link. The Texas Instruments 145406 has three drivers and three receivers, while the 145407 also includes +10 and -10 supplies, like the MAX232.

Just to make it interesting, sometimes DTE has to be connected to DTE, or DCE to DCE. Then the crossings actually have to be made in the connections. Also, the cable connector will be of the wrong sex at one end. This is easily handled by wiring two DB-25S's together with the connecting jumpers making the crosses, and the pin 7's, the grounds, connected togther. For connecting two DCE's, two DB-25P's are needed. In either case, connect 2-3, 3-4 and 6-20 (usually 6,8 and 20 are connected together). These adapters turn a DTE into a DCE, and vice versa, changing the connector sex appropriately, so a normal cable will work. In the early days, many serial interfaces were wired in strange and individualistic ways, making RS-232 interfacing an interesting puzzle.

Another sort of adapter turns a DTE into a DCE, and vice-versa, without a change in connector sex. A DB-25S and a DB-25P are wired together with 2-3, 3-4 and 6-20 interchanged. If a device is given the wrong connector sex, an adapter can be made to set things right. Say a DTE is given a DB-25S connector. Then we need two DB-25P's wired together with connections not interchanged.

Sometimes it is necessary to "fool" the handshaking to get communication going. To do this, use an adapter made from a DB25P and a DB25S, so it will not change sex. On the side where the handshaking has to be fooled, connect 4-5 and 6-20 with jumpers. Then the RTS output will be the CTS input, and the DTR output will be the DSR input, on DTE, with the opposite signals on DCE. This is useful when one side is controlled by software, and issues no handshaking signals, while the other side requires the handshaking signals to operate, but of course will still be controlled by software. Sometimes the handshaking has to be fooled on both ends.

An adapter useful in testing is the loopback adapter. It is made on a mating DB-25 connector, with jumpers between 2-3, 4-5 and 6-20. Any data output will come right back in. An ACIA is a full-duplex device, and can send and receive at the same time. When troubleshooting a serial link, a loopback adapter is a necessity. It is used to guarantee that each device can separately send and receive. When this is proved, it is only necessary to connect the proper wires.

To make things truly confusing, some cables have the signal transpositions included. That is, pin 2 at one end is connected with pin 3 at the other, and vice versa, though the DB-25 connectors may be of different sex. If they are of the same sex, the cable can clearly be used to connect DTE with DTE and DCE with DCE without adapters. Check any suspected cable with an ohmmeter to find out if it has transpositions (and if it does, give it to an enemy). Another treacherous cable does not have the full complement of 25 conductors (often indicated by the absence of pins in the DB-25P). It is best for any funny business to go on in the light of day with adapters. All you need are standard cables with 25 wires, and a DB-25S on one end and a DB-25P on the other, and a supply of DB-25S and DB-25P connectors, with spacers to hold two together.

Another very useful troubleshooting device has a DB-25S at one end, and a DB-25P at the other, with bicolor LED's to show the state of the lines. A red LED shows that the corresponding circuit is at MARK or negative, while a green LED shows that the circuit is at SPACE or positive. The state of the handshaking signals can be seen at a glance, while the TXD and RXD lights flicker when data is passing.


ACIA is an acronym for Asynchronous Communications Interface Adapter. Bytes written to it by the processor are converted to serial format and transmitted; data in serial format arriving from the line are converted to bytes and may be read by the processor. The ACIA stands between the computer busses and the line transmitters and receivers. We will describe the Motorola 6850 ACIA here; it is similar to the 6550 ACIA and the 8250 ACIA used with Intel processors. The ACIA is a UART (Universal Asynchronous Receiver and Transmitter) designed to be used with a computer bus rather than stand-alone.

The connections to the ACIA are shown in the diagram. At the left are the processor bus connections, on the right the serial link connections. The bus connections are the eight data lines, D0-D7, which are bidirectional. They must be connected to the data bus through a bus transceiver. The R/W' tells whether the bus cycle is a read or a write. The register select RS is connected to address bus A0. When A0 = 0, the control/status register is accessed. When A0 = 1 the data registers are accessed. φ0 is the strobe signal that latches data on its falling edge. The read or write is effective only when the chip selects are active. CS1 and CS2 are held permanently high on the 7710, while CS0' is connected to the DEVICE SELECT' for the slot the interface is in. This is an address decode for the range of 16 addresses assigned to the slot.

A data frame begins with a start bit when the line goes from MARK to SPACE for one bit period. Seven or eight data bits are then sent, low order first, followed by an optional parity bit that makes the total number of one bits even or odd, not counting the start bit. Finally, one or two stop bits are sent, to allow the receiver to reset for the next data frame (and perhaps for a computer to read the data). The line ends up in the MARK state again. Clocks at transmitter and receiver are independent, but run at closely the same rate so the bits are sampled at the proper times. Because the data frames start at arbitrary times, the transmission is called asynchronous. The bit rate N is the number of bits per second, so each bit is 1/N seconds long. The bits are timed by a square-wave clock signal applied to the ACIA, of a frequency N, 16N or 64N, selected by software when the ACIA is initialized. Usually, the transmit and receive clocks are the same. The 7710 offers 16 different bit rates, from 50 to 19,600, selected by 4 logic switches. The transmitter is inhibited when CTS' is high, and the receiver is inhibited when CD' is high.

Synchronous serial links transmit the clock on a separate line. Adapters are available for this transmission mode as well. Synchronous links are generally capable of higher transmission rates.

The 6850, like most ACIA's, is double-buffered. This means that a received byte is transferred to a holding register as soon as it is complete, and the ACIA can begin to receive another one immediately. This gives the processor the full data frame time to read a received byte and dispose of it, before waiting for the next one. The same thing happens at the transmitter, where a byte written to the ACIA is transferred to the transmit register as soon as the previous byte has been transmitted, leaving the input register available to be loaded, so the transmitter need not wait for a byte.

The command register is loaded by writing a byte to an even address on the 7710. Bits 1 and 0 control the clock division ratio by 00 divide by 1; 01 divide by 16; and 10 divide by 64. 11 is the master reset, overriding all other bits. The master reset must be used on power-on; it is a good idea to use it every time the ACIA is prepared for use. Bits 4,3 and 2 set the data format. 100 is 8 data bits and 2 stop bits; 101 is 8 data bits and 1 stop bit; there is no parity bit in either case. Bits 6 and 5 control the RTS output and the transmitting interrupt. 00 gives RTS low and no interrupt, while 10 gives RTS high and no interrupt. Bit 7 is the receive interrupt enable bit. It is 0 to disable the receiving interrupt. Putting all this together, we can reset with 000000011 or $03, set 8 bits, 2 stop bits, no interrupts, RTS low and clock divide by 16 with 00010001 = $11. RTS is high with 01010001 = $51.

ACIA status is obtained by reading a byte from an even address. Bit 0 is Receive Data Register Full, RDRF. When it is 1, there is a byte to be read. Bit 1 is Transmit Data Register Empty, TDRE. When it is 1, a new byte can be written to the data register. Bit 2 gives the CD' level, while bit 3 gives the CTS' level. Bit 4 signals a framing error, when the stop bits do not appear as expected. Bit 5 signals an overrun error, when a new byte is received before the previous one has been read. Bit 6 is high when the parity of the received byte does not agree with the parity set. Since we are not using parity, it has no effect. Bit 7 shows when an interrupt request has been issued by the ACIA; a 1 means that an interrupt request is active. Generally, it is necessary to check only bits 0 and 1 when reading or writing a data byte.

The Apple Expansion Slot

The Apple II has seven 50-contact card edge connectors on the main board, called expansion slots. They give access to the address bus, data bus, control signals and power supplies to a card plugged into them. The Apple also supplies individual address decodes to each slot, so that the plug-in cards need not decode their own. Addresses in C000-CFFF are used for I/O by the Apple. If n is the slot number, addresses Cn00-CnFF are assigned to slot n, and any reference to them causes the I/O SELECT' signal to go low on this slot. This block of 256 bytes is intended to access ROM on the card, which contains the driver routine for the slot. Additionally, the 16 addresses C0n'0-C0n'F, where n' = n + 8 activate a DEVICE SELECT' signal on slot n. This block of addresses is used to perform the actual byte I/O. Each of the 7 slots has its own two enables of this kind. In addition, there is a single large 2KB block C800-CFFF that can be used to access a larger program in ROM. Any reference to this block pulls the signal I/O STROBE' low. Each slot must respond to the address CFFF by disabling any such ROM. The slot desiring to use this space can then enable its own ROM without interference from other slots. The ROM enable is provided by a SR flip-flop cleared by the CFFF reference and set by (say) a C0nX reference. Since address signals A0-A7 can be applied to a ROM enabled by CnXX, at most a card may have to decode only the 16 addresses C0n'0-C0n'F.

Not only does each slot have 256 memory locations reserved for ROM, but also eight RAM locations at $0m78 + n and $0mF8+ n, where m = 4, 5, 6, 7 and n is the slot number. The 7710 card uses several of these for parameters related to text lines. These locations are "holes" in the display page buffers.

The IBM PC copied the Apple's expansion slots, but the provision of address decodes was not practical. The use of the memory space was more flexible, and the 8088 processor had a separate I/O address space. Therefore, each slot was left to its own devices in address decoding. It would have been nice to have had some I/O space decodes specific to each slot, but this was not done. It is just as easy to study things like an ACIA on the PC I/O bus as in an Apple slot, but with a little more circuitry. Prototyping cards are still available for the PC I/O bus, since it became the ISA bus in later days. For the Apple, a Vector Plugbord with 72 contacts (Mouser 574-3719-1) can be cut down to 50 will do. This board is 6.5" high, so must also be cut down if it is to fit with the cover on.

For my exercises, I had a California Computer Systems Model 7710 asynchronous serial interface board. This is essentially a 6850 ACIA interfaced with the bus, with a 256KB ROM. Let's assume that this board is in slot #4, so that its ROM is accessed at C400-C4FF, and the ACIA at C0C0-C0CF. If you are using some other slot, the addresses should be adjusted accordingly. Instead of decoding the four low address lines, A0 is applied to the register select pin of the ACIA. All even addresses access the control/status register, and all odd addresses the data registers. The driver routine is easily listed on the screen by executing C400L. It is also given in the Owner's Manual. Studying this routine is an excellent exercise in machine-language programming.

Let's consider how to ouput a byte typed at the keyboard. When you type a key, the ASCII code for the key is loaded in the accumulator A, and JSR COUT is executed. COUT is FDED, a location in the Monitor, where the instruction JMP(CSWL), 6C 36 00. This jumps to the routine whose address is in the location $36-$37 in zero page. This routine may be COUT1, at FDF0, which will send the byte to the screen. This routine must handle the cursor (the place on the screen where output is placed), starting new lines when necessary and scrolling the old ones. It writes to display memory, and finally returns with an RTS instruction, so that the return address pushed by the JSR is popped and we return to the calling routine. The Apple displays bytes with bit 7 set in normal video. If bit 7 is 0, the display will blink. Older Apples only displayed upper case, where the bytes corresponding to A-Z had bit 6 set. Starting with 7-bit ASCII, this can be done by ORing a byte corresponding to a-z with $A0.

When DOS is active, the address at $36 is changed to the address of the character output routine in DOS, which passes it on to COUT1 when DOS has done what it has to do.

To output a byte to the ACIA, the address at $36 must be changed to the address of the driver routine. This can be done with the Applesoft command PR#4, which changes $36 to point to the address C400, the first byte in the card ROM. To keep DOS in the picture, CHR$(4) (ASCII EOT) should first be input. In an Applesoft PRINT statement, this is PRINT CHR$(4);"PR#4". Now when you type a key, the ASCII code will be loaded into A and a JSR to C400 will be done to dispose of it.

When the driver program is called at C400, it recognizes that it is being opened for use. It must set up entry points for subsequent input and output, find out in which slot it is located (so that it knows the proper addresses for the ACIA), and initialize the ACIA. When entered at 00, a cold entry, the driver sets the V flag to show that this is the first access. There is no SEV instruction, so the V flag is set by BIT RETURN. RETURN is a Monitor location that contains an RTS instruction. It is used here because its address, $FFCB, has a 1 in bit 6, which is put in the V flag by BIT. This is followed by BVS COM, which is always taken. COM is the beginning of the routine that saves processor registers and finds out which slot the card is in, which is always executed when the driver is called.

Following this are the two warm entry points. At 05 is a CLC instruction, and at 07 is a SEC. C = 0 indicates output, while C = 1 indicates input. At 06, following the CLC, is a DFB $B0, which puts a $B0 in the program. This is the opcode for a BCS. The following byte, $38, is taken as the second byte of the instruction by the processor. Since C = 0, the branch is never taken, and execution proceeds at 08, where there is a CLV. This clears the V flag if it is set, and shows that this is a warm entry, not an initialization. This is a "trick" to skip the SEC instruction when entry is made at 05. A BCC COM, or 90 01, could be used instead. The trick only saves one byte and one cycle, but saving a few bytes is important when cramming a driver program into 256 bytes.

Both of the warm entry points, then, fall into the COM procedure. After saving A, X, Y and P on the stack, an SEI disables interrupts. Now the card finds out where it is. A JSR RETURN goes to $FFCB and comes right back. The stack pointer S now points to the last item popped, which is the high byte of the return address. Since we are in slot 4, this will be C4. We do a TSX, and then a LDY $100,X to put C4 in Y. Now we do 4 PLA's that bring the stack back to what it was at COM, leaving the data in A. A TXS restores the stack pointer to what it was after the RETURN, and now we PHA to save the data. We put C4 in A with TYA, and shift out the C with 4 ASL's, leaving 40. TAY puts this in Y, where it will be used to create the I/O address. We can now PLA to put P on the stack top, PLP to restore the processor status, and finally PHA to save the data again. Now, if V = 0, we branch to the IO routine. The stack operations cannot be understood by just reading them; a good stack diagram can be used to follow the stack through the program.

If V = 1, the ACIA is to be initialized, and the warm entry points are to be set. ACIA master reset is accomplished by LDA #$03, STA $C080,Y. Note that C080 + 40 = C0C0, the proper address for this slot. The CCS program has $23 instead of $03, but there is no reason for the difference. Then, LDA #$11, STA $C080,Y sets 16x clock, no interrupts, RTS high, 8 data bits, no parity, 2 stop bits. After this, we CLV, and go on to the vectors. First, KSWL at $38 is checked to see if it contains 00, and then KSWH at $39 to see if it contains $C4. If either is true, we skip input initialization and go to output initialization. If we continue with input initialization, 00 is stored in the lower-case mask at $6F8 - $C0 + $Cn with STA $6F8 - $C0,Y. A will contain 0 at this point, read from KSWL. Now we fix this with LDA #7, STA KSWL. Now we SEC so that we skip the next instruction, which is a BCC to the output routine. This branch is also taken by a warm entry that skips the initialization, provided carry is clear, indicating output.

Now we finally reach the routine that actually does the input. First, we have to wait until bit 0 of the status is set. This is done with the loop INPUT LDA $C080,Y, LSR A (to put bit 0 in C), and BCC INPUT. This loop falls into PLA (which merely keeps the stack honest), and then LDA $C081,Y gets the data from the ACIA. ORA #$80 sets bit 7 to keep the Apple display happy, and PHA saves the data on the stack. If it is a line feed, it is ignored and we go back to get another byte, with CMP $8A, BEQ INPUT. Bit 7 will already have been set. Now, proceeding, we PLA to get the data back, and CMP #$E0 to see if it is a lower-case letter. If it is, we EOR $6F8 - $C0,X to change it to upper case. { is also changed to [, | to \, } to ], ~ to ^, and DEL to _. It would be easy to limit the change at "z" but this is enough for the Apple, which does not use the last 5 characters.

Now we finish up. from input, we restore the stack pointer with TSX, INX, INX, INX, STA $100,X. Then we restore the registers as they were at entry, with PLA, TAY, PLA, TAX, PLA except that A now contains the data read from the ACIA. The program ends with RTS.

The output initialization routine begins by storing 5 in CSWL with LDA #5, STA CSWL. Then LDA #FF, STA $5F8 - $C0,X sets the maximum line length at 255 characters. LDA #0, STA $778 - $C0,X initializes the character count to zero. All of these actions are Apple-specific. The output routines handles other such duties, which will not be specifically described here. The actual output is done by the routine that begins OUTC LDA $C080,Y, AND #3, BEQ OUTC. This waits for either transmit register empty or receive register full. Then AND #1, BNE INCHR goes to the input routine if input is present. This routine checks to see if the character is ^S. If it is, output is halted until another character is received. These characters are not returned, since they are merely handshaking, not data. PLA now puts the data in A, and STA $C081,Y sends it to the transmit register. This routine replaces the one sending output to the screen, and must handle all the Apple-specific functions included there. In particular, linefeed, carriage return and backspace must be handled, and generated when necessary. When this is done, a PLA precedes the same exit routine as for input.

A driver for a utility serial link need not be nearly as complicated as the one the 7710 uses. We may simply want bytes written at one end to be received by the other, with no attention to case, bit 7's, carriage returns and line feeds. The initialization can be carried out in the same way, with the establishment of warm entry points. For handshaking, we could check the state of CTS using the status byte, and transmit only when CTS is active.

Monitor Exercises

A lot can be learned by sending and receiving bytes using the Monitor. Let's assume we have a 7710 in slot 4 for concreteness. Very similar exercises can be carried out with any ACIA on any bus. For example, an ACIA on the IBM PC bus can be exercised in DEBUG. The card should have an attachment showing the state of the RS-232 circuits, and a loopback adapter.

The driver program for the 7710 can be listed with *C400L (the monitor prompt * is shown). The first thing to do is to initialize the ACIA with *C0C0:03. Next, set the mode with *C0C0:11, and again with *C0C0:51, to see RTS change. With the loopback adapter, RTS and CTS will, of course, change simultaneously. If the loopback adapter is removed, either the light for RTS (with DTE) or the light for CTS (with DCE) will remain, while the other will be off. This is how DTE and DCE can be distinguished.

Now examine the status byte with *C0C0, noting particularly the two lowest-order bits. They are probably 10, showing the transmit register ready and the receive register empty. Now send a byte with *C0C1:55 (say). The two lowest-order bits of the status byte will now be 11, showing a character has been received (thanks to the loopback adapter). Read the character with *C0C1, and you should get 55. The status bits will now be 10, showing the receive register is now empty again. The transmit register ready bit will always show as 1 with this manual operation, since any byte written to the transmit register is very quickly shifted out. Even at the lowest speed of the 7710, 50 baud, a byte is gone in about 0.2 seconds.

Next, some of the other bits in the status byte can be studied. Bits 6 and 7 will remain at 0, since we are not using parity or interrupts. Bit 5 is framing error, which is easy to produce. First, check the status byte. Then, write a byte to the ACIA twice in a row, without reading it, and check the status byte again. Bit 5 should now be set. See if it clears when the received data is read with *C0C1. We cannot easily produce a framing error, so bit 4 will remain 0. Bit 3 reflects the state of CTS. Change the state of RTS to see how the flag behaves. The 7710 is configured as DCE, so exchange RTS and CTS in the above sentences. Bit 2 does the same for DTR/DSR. We can modify the loopback adapter to allow the connection of pin 20 (on the 7710; pin 6 on DTE) to +5 or ground so that we can observe the flag change. Note that we can affect the state of one output bit on the 7710, and read the states of two input bits.

Study the effect of the level at pin 4 (which is connected to CTS' on the 7710) on the transmitter. When the CTS' pin is high (RS-232 SPACE) the transmitter is inhibited. Now after you write a byte to the transmit register, it will stay there and the TDRE flag will remain at 0. When you change the state of CTS' (RTS on the 7710), the transmitter will wake up and TDRE will quickly become 1. If you have arranged to control the state of pin 20, you can observe a similar effect on the receiver. By using these signals, transmission can be controlled.

Hardware Considerations

A serial terminal can be made from a UART like the AY-3-1015 without the need of a computer. We have seen above how an ACIA is used with a computer to provide a very flexible serial terminal. A serial port may be built in to a computer, but more often is provided by a plug-in expansion card. A few hints on how to make such a board are presented here. It is not at all difficult to do this for the PC's ISA bus, and probably not with the newer PCI bus, but I have not yet attempted this because of the lack of information.

The computer's data bus can certainly write to an ACIA or other peripheral directly, but the ACIA cannot be heard in the other direction, so that a data bus buffer or transceiver is necessary. A suitable chip for this is the 74LS245, though quite a number of similar chips have been available. Such transceivers have eight bidirectional buffers controlled by the R/W' signal and an enable E'. On the Apple, E' should be connected to an AND of DEVICE SELECT' or I/O SEL' so that the buffer will be active whenever the board is addressed. On the PC, E' must be obtained from a memory decode on the board. The A bus, pins 2-9, are connected with the ACIA and other on-card devices interested in data, while the B bus, pins 11-18 is connected to the data bus, D0-D7.

The TTL-RS level interface can be made by any of the chips described above. It is normally more convenient to use a MAX232 or 145407 that generates the voltages required if they are not available on the computer bus. A MAX232 serves only the necessary minimum number of lines, but the 145407 includes another input and output that can be used for any purpose.

The standard specifies that the receiver input resistance shall be no larger than 7 k&Ohms;, and the transmitter slew rate not more than 20 V/μs, to prevent inductive kicks. The input resistance specification is usually quite well met, but the slew rate of the 1488 and similar transmitters is much larger. A 330 pF capacitor across the output limits the slew rate acceptably.

A processor can be programmed to imitate an ACIA rather easily, using its own clock for timing. The processor can even determine the bit rate to use by analyzing a received data frame. However, when the processor has more important things to do, timing is generally created by a clock oscillator, and applied to the ACIA. For example, a bit rate of 2400 bits/sec requires a frequency of 16 x 2400 = 38.40 kHz, if the ACIA is programmed for a 16X clock. These frequencies are produced by counting down a crystal oscillator. If the crystal frequency is 2.4576 MHz, dividing by 64 gives exactly 38.4 kHz. Since the "baud rates" are related by factors of 2, a binary counter with a crystal oscillator of this frequency may be used.

A bit rate generator includes a crystal oscillator and a counter with several outputs, or a divisor controlled by input bits, on a single chip. The 16-pin Motorola 145411 uses a 1.8432 MHz crystal to make 8 bit rates from 2400 to 153,600 (at 16X clock). With a 1X clock the rates are from 150 to 9600 bits/sec. The 24-pin 14411 makes 16 bit rates. Sometimes the frequencies are not exact, but a difference of less than 5 percent is of no consequence.

Some chips may consume so much power on standby that it may be desirable to power them down unless enabled. This is easily done with a PNP saturated switch, using a PN2907 or a 2N4403, as shown in the figure. The base should be driven by a 7407, 74S09 or equivalent, since about 18 mA is required for hard saturation, and a normal LSTTL output can provide only 8 mA. The collector will then be no more than 0.1 V below the emitter. Depending on the output current required, the base drive may be made less by increasing R2 (base drive = 4.0/R2).

It must be remembered that with the Apple II, the power must be off before any cards are removed or inserted. There is a high probability of a dangerous short at the card fingers that may destroy memory. Of course, removing power before changing cards is good practice with any computer. The RS-232 link is designed to resist shorts between circuits, incidentally, so connections can be changed under power.


It is easy to see from these references that computer documentation has declined precipitously in information content since the early 80's. It is no longer possible to get enough information to study or experiment from the information furnished. This makes early equipment particularly valuable for learners.

California Computer Systems, Owner's Manual, Model 7710 Asynchronous Serial Interface, No. 42000036-01 (Sunnyvale, CA: CCS, 1981).

Apple Computer, Apple IIe Reference Manual (Cupertino, CA: Apple, 1982).

Apple Computer, Reference Manual Addendum: Monitor ROM Listings (Cupertino, CA: Apple, 1982).

Motorola, Motorola Microprocessors Data Manual (Motorola, Inc., 1981). pp. 4-527, -535. The 6850 ACIA.

IBM, IBM Personal Computer Technical Reference (Boca Raton, FL: IBM, 1983). pp. 1-223, -250. The 8250 ACIA and the IBM I/O Bus.

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Composed by J. B. Calvert
Created 11 September 2004
Last revised 12 September 2004