Signal Switches and Sample-and-Hold Circuits

Signal Switches

A mechanical switch has the desirable characteristics of practically zero resistance when ON, and practically infinite resistance when OFF, providing a complete break in the conducting path. However, it has to be operated mechanically and slowly, bounces when closed, and deteriorates with use. We have already discussed the transistor switch, which is close to ideal and can handle large currents, but nevertheless has a finite voltage across it when closed, and does not give perfect isolation when open. On the other hand, it operates very rapidly, and does not deteriorate with use.

Another class of switches can be called signal or analog switches. Here, we do not handle power but signal levels, and what is desired is a high resistance, almost perfect isolation, when OFF. A reasonable amount of resistance can be tolerated in the ON state, up to a few hundred ohms or so. The switch should be able to control signals at any reasonable voltage level (which is why they are called analog) and not be tied to ground or the positive supply. FET's can be used for this purpose, since they have a very high resistance in cutoff, and a rather small resistance between drain and source when conducting.

A JFET switch is shown at the right. The MPF102 can be used, since it is a typical JFET, and it does not matter whether source or drain is the input, since the JFET is practically symmetrical in this application. The leads to the MPF102 are in the order DSG when looking at the flat side with the leads downward. The reverse breakdown voltage for the gate is guaranteed greater than 25V, so it is all right here where the maximum to which it could be exposed is 24V, using ±12V supplies. The signal is assumed to range from 0 to 12 V. In the ON state, the source and gate are connected by the 1M resistor, which gives a zero bias. Care must be taken that the drain does not become too positive with respect to the source, or the gate will become forward-biased. The only effect here would be to pull the gate negative, so no damage would be done. In the OFF state, the gate is pulled to -12V. Since the pinchoff voltage for the MPF102 is guaranteed less than 8V, this will be plenty to keep the JFET off for the full signal range. Actually, the signal could go at least 4V negative without problems. Measure the input and output voltages of this circuit, and estimate the ON resistance of the JFET switch. At a signal voltage of about 5V, I found 167Ω, quite negligible compared to the 10k load.

A MOS transistor can also be used as a switch. The enhancement type that is normally nonconducting and requires to be pulled ON is used. The voltage between gate and channel, which affects the conductivity, varies with the signal level. To give conductivity for any signal level, two MOS transistors are paralleled, one PMOS and one NMOS, so that either one or the other is on for any signal level. The control voltage is inverted for one of the transistors. By careful design, the ON resistance can be made low for any signal voltage. The CMOS process is ideal for making these switches, and the 4000-series CMOS logic included analog switches from the first. The 4016 and 4066 are quad analog switches, the 4066 being a somewhat improved version of the 4016, and both are available in HC logic, in even more improved form, as the 74HC4016 and 74HC4066.

Connections for the 4066 (and 4016) are shown at the right. The four switches are independent, but have a common power supply. The dot on one of the in/out leads to each switch shows similar ones. The switches are bilateral, meaning that either of the in/out leads can be the input or output, but the two kinds of leads are connected differently on the chip. It does not matter much which you use, however. The recommended power supply is from 3 to 15V (HC 3 to 12V), and like all CMOS chips, it works better the higher the supply voltage. 12V is completely satisfactory. The data sheet does not give any maximum currents through the switches, but the voltage drop should be held to less than about 0.7V, which corresponds to about 10 mA. The ON resistance of the 4016 is about 200Ω, of the 4066 80Ω, and of the HC4066 about 60Ω, larger for smaller supply voltages. Test one of the switches, using a 1k load. The signal voltage should never go outside the power supply range. All CMOS devices, including these, are susceptible to damage by electrostatic discharge, so care should be taken. The HC packages are better protected.

Sample-and-Hold

It is often desired to take a "snapshot" of a signal level at a particular time, and save it for later analysis. This is particularly important in analog-to-digital conversion, where changes in the input during the conversion period may lead to quite erroneous results. The circuit for doing this is called a sample-and-hold. The idea is to save the value as the voltage across a capacitor. Using FET's, we can isolate the capacitor from discharge, while reading its value at leisure.

An illustrative sample-and-hold circuit is shown at the left, made from discrete components. The dual op-amps in an LM412 are ideal for the purpose, because their input bias currents are practically zero. An MPF102 is used to isolate the capacitor from the source used to charge it. For our purposes, we can command sample and hold by connecting a wire manually to -12 for HOLD, and leaving it disconnected for SAMPLE. For a practical circuit, we would make better arrangements for the control. Note the back-to-back signal diodes at the output of the left-hand op-amp (any diodes can be used). The purpose of these diodes is to "catch" the output when the feedback loop is broken when the JFET turns OFF. The 33k resistor isolates this action from the output feedback loop. If these diodes are not present, the op-amp saturates at the supply rail and the JFET will not turn off. Test the circuit, make sure it HOLDs properly, and observed the droop of the output. I found a droop of 0.23V in 5 minutes, or a rate of just 0.77 mV/s, corresponding to a leakage of 77 pA! This is really pretty good.

The choice of hold capacitor is important. The leakage of electrolytics and the transient behavior of ceramics rule them out completely in this application. The best choice is probably polypropylene, which I used, and after that polystyrene or Mylar. Polycarbonate is much inferior to all of these. The greatest problem (after leakage, which should be practically zero) is dielectric hysteresis in which the voltage changes on charge and discharge are not the same. There is also dielectric absorption, where there is a "memory" of past states. A capacitor freshly discharged may acquire a small voltage as time goes by. All of these phenomena are the result of the complexity of dielectric structure and behavior.

Some properties of sample-and-hold circuits are important in critical, dynamic applications. The hold step is the change in output voltage when the circut is switched OFF, the result of various capacitive effects. The settling time is the time required after the HOLD command for the output to stabilize. The aperture time is the time after the HOLD command at which changes in the input have no effect. The aquisition time is the time at which the ouput settles after a change at the input. Finally, the dynamic sampling error is the difference between the voltage held and the instantaneous input voltage at the instant of the HOLD command. Our experiment is not set up to measure any of these accurately. Hold steps are on the order of mV, aquisition times of μs.

Everything necessary for a sample-and-hold except the hold capacitor can be put on on chip, so monolithic sample-and-hold circuits, like the LF398, are available and very easy to use. The sample/hold command is given through a digital logic level, so these circuits interface directly with logic. The LF398 has a hold step of less than 1 mV, and an aquisition time of 4 μs. Its input resistance is high, its output resistance low. See Sample-and-Hold for additional information.

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Composed by J. B. Calvert
Created 14 August 2001
Last revised 30 July 2002